The present invention relates generally to testing of printed circuit boards, and more particularly, relates to a method and apparatus for implementing finished printed circuit board high potential testing to identify latent defects.
Current and future high performance computer systems and server systems rely on both large scale packaging of multiple high density interconnect modules and printed circuit boards (PCBS).
Printed circuit boards (PCBs) are constructed through the use of fibrous glass cloth and resin systems, along with copper foils. This construction has an inherent risk associated with the bonding of the resin system to the glass fiber as well as the ability for the resin to adequately fill areas where copper is etched away by design. If insufficient bonding or fill has taken place during the lamination processes, a path for future ionic and/or copper growth exists. This may at some point result in latent failure in the customer environment.
FIG. 1 illustrates a conventional printed circuit board (PCB) in a cross sectional view not to scale. As shown in FIG. 1, multiple plated through holes are provided for implementing connections for power and ground planes. Multiple adjacent opposing voltage surface features are disposed on the PCB top and bottom surfaces. Defects including voids and a crack are shown in FIG. 1 that can result in paths for future ionic and/or copper growth.
Conventionally finished PCB high potential testing typically is limited in the maximum applied voltage by the proximity of the surface features. The closer the surface features, the easier for surface arcing to occur, resulting in false failure. Surface arcing between adjacent opposing voltage surface features results, for example, with an applied test voltage above approximately 500 volts direct current (DC). Latent defects, such as the illustrated void and crack defects, are not detected when limiting the finished PCB testing to less than 500 VDC being applied.
A need exists for an improved mechanism for implementing the testing of finished printed circuit boards. It is desirable to perform testing of finished printed circuit boards to identify latent defects.
A principal object of the present invention is to provide a method and apparatus for implementing finished printed circuit board high potential testing to identify latent defects. Other important objects of the present invention are to provide such method and apparatus for implementing finished printed circuit board high potential testing to identify latent defects substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing finished printed circuit board high potential testing to identify latent defects. A printed circuit board to be tested includes adjacent surface features having opposing applied voltages. An electrically non-conductive material is disposed between at least some of said adjacent surface features. A predefined voltage potential is applied between predefined power connections of the printed circuit board to identify the latent defects. The electrically non-conductive material prevents surface arcing between the adjacent surface features at the applied predefined voltage potential.
In accordance with features of the invention, the applied predefined voltage potential for finished printed circuit board testing is, for example, 1500 VDC or higher and surface arcing is avoided.